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Proceedings Paper

40-Gbps monolithically integrated transceivers in CMOS photonics
Author(s): T. Pinguet; B. Analui; G. Masini; V. Sadagopan; S. Gloeckner
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Paper Abstract

We report on the development of single-chip, monolithically-integrated 40 Gbps transceivers built in a 130 nm SOI CMOS process as part of Phase II of the DARPA EPIC program. In this talk we give an overview of the system architecture, including the transmit and receive paths as well as the control systems. We report on the performance of the individual building blocks, and discuss a scaling to 100 Gbps and beyond single-chip transceivers built in CMOS photonics.

Paper Details

Date Published: 26 February 2008
PDF: 14 pages
Proc. SPIE 6898, Silicon Photonics III, 689805 (26 February 2008); doi: 10.1117/12.766865
Show Author Affiliations
T. Pinguet, Luxtera (United States)
B. Analui, Luxtera (United States)
G. Masini, Luxtera (United States)
V. Sadagopan, Luxtera (United States)
S. Gloeckner, Luxtera (United States)

Published in SPIE Proceedings Vol. 6898:
Silicon Photonics III
Joel A. Kubby; Graham T. Reed, Editor(s)

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