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Proceedings Paper

A real-time bit-serial rank filter implementation using Xilinx FPGA
Author(s): Chang Choo; Punam Verma
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Paper Abstract

Rank filter is a non-linear filter used in image processing for impulse noise removal, morphological operations, and image enhancement. Real-time applications, such as video and high-speed acquisition cameras, often require the rank filter, and the much simpler median filter. Implementing the rank filter in hardware, can achieve the required speeds for these applications. Bit-serial algorithm can increase the speed of rank filter by eliminating the time-consuming sorting network. In this paper, an 8-stage pipelined architecture for rank filter is described using the bit-serial algorithm. It also includes an efficient window extraction and boundary-processing scheme. This rank filter design was simulated and synthesized on the Xilinx family of FPGAs. For 3×3 window size, the maximum operating frequency achieved was 75 MHz on a low-end device XC3S200 of Spartan-3 family, and 180 MHz on a high-end device XC4VSX25 of Virtex-4 family. For 5×5 window size, the maximum operating frequency achieved was 67 MHz on XC3S200, and 138 MHz on XC4VSX25. With a pixel filtered out at every clock cycle, the achieved speeds are sufficient for most of the video applications. The 3×3 window size design used 31% of slices on XC3S200, and 5% on XC4VSX25. The 5×5 window size design used 60% of slices on XC3S200, and 11% on XC4VSX25. This IP design may be used as a hardware accelerator in a fast image processing SOC.

Paper Details

Date Published: 26 February 2008
PDF: 8 pages
Proc. SPIE 6811, Real-Time Image Processing 2008, 68110F (26 February 2008); doi: 10.1117/12.765789
Show Author Affiliations
Chang Choo, San Jose State Univ. (United States)
Punam Verma, San Jose State Univ. (United States)

Published in SPIE Proceedings Vol. 6811:
Real-Time Image Processing 2008
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

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