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Proceedings Paper

A complementary logic partitioning algorithm for a library-free logic synthesis paradigm
Author(s): Hisham El-Masry; Dhamin Al-Khalili
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Paper Abstract

This paper presents a novel approach for technology partitioning in a library free paradigm based on the use of virtual cells. Previous methods for library free logic partitioning rely on creating the largest possible partitions from a user defined criteria, predominately the stack length of the transistor level implementation. However, these methods can cause conflicting structures, defying the AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) representations that are used as templates for the virtual cells. The Complementary Logic Partitioning (CLP) algorithm, defines a partition as consisting of only two hierarchical levels of complementary nodes (AND and OR), as well as using the logical effort model for the migration of inputs to optimize the partitions to meet both the user defined limiting criteria and minimize the delay of the inputs. The CLP algorithm is compared against Synopsys' Design Compiler using Artisan standard cell library for a set of MCNC '91 benchmarks. Preliminary simulation results based on TSMC's 0.18 micron CMOS technology, show a reduction of more than 50% in the critical path delay can be achieved with CLP.

Paper Details

Date Published: 21 December 2007
PDF: 8 pages
Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 67980N (21 December 2007);
Show Author Affiliations
Hisham El-Masry, Royal Military College of Canada (Canada)
Queens Univ. (Canada)
Dhamin Al-Khalili, Royal Military College of Canada (Canada)

Published in SPIE Proceedings Vol. 6798:
Microelectronics: Design, Technology, and Packaging III
Alex J. Hariz; Vijay K. Varadan, Editor(s)

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