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Proceedings Paper

Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells
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Paper Abstract

DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful, these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness. An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and silicon experiment results will be presented.

Paper Details

Date Published: 30 October 2007
PDF: 9 pages
Proc. SPIE 6730, Photomask Technology 2007, 67300X (30 October 2007); doi: 10.1117/12.747021
Show Author Affiliations
Kuang-Kuo Lin, Chartered Semiconductor Manufacturing, Inc. (United States)
Ban P. Wong, Chartered Semiconductor Manufacturing, Inc. (United States)
Frank A. J. M. Driessen, Takumi Technology Corp. (United States)
Etsuya Morita, Takumi Technology Corp. (United States)
Simon Klaver, Takumi Technology Corp. (United States)

Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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