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Proceedings Paper

Intel's AMT enables rapid processing and info-turn for Intel's DFM test chip vehicle
Author(s): Hazem Hajj
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Paper Abstract

Transistor dimensions are quickly approaching atomic levels. Metrology is already a challenge. Several technologies have evolved to keep pace such as scatterometry and bare wafer inspection. Lithography critical dimensions, registration and pitch are the forefront of dimensional scaling challenges. Variability at these dimensions can limit function, performance, yield and profitability with design for manufacturing (DFM) challenges. Intel's integrated device manufacturing (IDM) model has enabled many technologies and disciplines to come together to provide the most cost effective and optimal solutions to Moore's law scaling challenges. Intel's Automated Manufacturing Technology (AMT) capabilities play a significant role in enabling optimal Moore's law scaling solutions. The information turn cycle starts with the definition of the technology Test Chip and ends with the analysis of results from end of line (EOL) metrology. We will discuss the relevant DFM elements of AMT to enable: test-chip setup, computational lithography and validation, product & process modeling and setup, intelligence and control to minimize variability, rapid yield learning, and rapid product design learning.

Paper Details

Date Published: 30 October 2007
PDF: 13 pages
Proc. SPIE 6730, Photomask Technology 2007, 67300Q (30 October 2007); doi: 10.1117/12.746844
Show Author Affiliations
Hazem Hajj, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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