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Proceedings Paper

Database and data analysis strategy for multi-designer testchips
Author(s): Wojtek J. Poppe; Patrick Au; Darshana Jayasuriya; Andrew Neureuther
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Paper Abstract

A database and data analysis strategy is proposed for multi-designer test chips that involve a wide array of different test structures aimed at process characterization. The database described in this paper has been custom built for the multi-student FLCC testchip that has six contributing students and over 15,000 individually probably transistors/test structures. It has an interface with the Parametric Yield Simulator (PYS) that drives simulation parameters and automatically populates the database with simulation results of each test structure at the specified process conditions. A well-designed database forces structure into measurement and design related data, but includes enough flexibility as to adapt to different types of test structures and experiments. The database is split into four separate sections that store description of test structures, simulated results, experiment results, and process conditions. All data is centrally located and web accessible for easy access from any computer with Internet access. Simulation results can be uploaded from the server running the PYS, experimental results can be uploaded directly from the lab and data can be compared and queried by all users of the database. Data analysis strategies can be compared and reused as queries and data analysis results can be shared among users through the website. Queries can be saved, loaded, rated, and reused, so even novice SQL users can utilize advanced queries. Advanced queries form the basis of a strategy that first identifies good process monitors based on simulation results and then uses them to extract process conditions from electrical measurements via an iterative process. This paper describes strategies that can be used to help facilitate collaboration and hence leverage the benefits of combining multiple sets of test structures from different designers on one chip.

Paper Details

Date Published: 1 November 2007
PDF: 12 pages
Proc. SPIE 6730, Photomask Technology 2007, 67303T (1 November 2007); doi: 10.1117/12.746739
Show Author Affiliations
Wojtek J. Poppe, Univ. of California at Berkeley (United States)
Patrick Au, Univ. of California at Berkeley (United States)
Darshana Jayasuriya, Univ. of California at Berkeley (United States)
Andrew Neureuther, Univ. of California at Berkeley (United States)

Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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