High data transfer rate has been demanded for data storage devices along increasing the storage capacity. In order to increase the transfer rate, high-speed data processing techniques in read-channel devices are required. Generally, parallel architecture is utilized for the high-speed digital processing. We have developed a new architecture of Interpolated Timing Recovery (ITR) to achieve high-speed data transfer rate and wide capture-range in read-channel devices for the information storage channels. It facilitates the parallel implementation on large-scale-integration (LSI) devices.

Date Published: 17 July 2007
PDF: 6 pages
Proc. SPIE 6620, Optical Data Storage 2007, 66200Y (17 July 2007); doi: 10.1117/12.738923

Published in SPIE Proceedings Vol. 6620:
Optical Data Storage 2007
Bernard Bell; Takeshi Shimano, Editor(s)