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Proceedings Paper

Warpage of thin wafers using computer aided reflection moire method
Author(s): Chi Seng Ng; Kok Yau Chua; Meng Tong Ong; Yoke Chin Goh; Anand K. Asundi
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Paper Abstract

To cope with advances in the electronic packaging industry, thinner wafers are being widely employed to produce thinner packages. However, this has lead to an increase in random cracks during the wafer singulation process, thus reducing the yield of the overall production. Large stresses are induced particularly during backside metal deposition. The wafers bend due to these stresses. This residual stress due to warpage lead to cracks which will severely re-orient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. In this study, Computer aided reflection moiré technique is adapted to further investigates the warpage induced on wafers with different backside metallization (bare silicon, AuY, AuX). The backside metal on the wafer is then etched to remove the residual stress. Residual stress due to the effect of warpage caused by different backside metallization has been experimentally investigated and compared. Applicability of this technique to correlate with the random crack in the die is further validated.

Paper Details

Date Published: 11 September 2007
PDF: 11 pages
Proc. SPIE 6672, Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies III, 667203 (11 September 2007); doi: 10.1117/12.732783
Show Author Affiliations
Chi Seng Ng, Infineon Technolgies (Malaysia)
Nanyang Technological Univ. (Singapore)
Kok Yau Chua, Infineon Technolgies (Malaysia)
Meng Tong Ong, Infineon Technolgies (Malaysia)
Yoke Chin Goh, Infineon Technolgies (Malaysia)
Anand K. Asundi, Nanyang Technological Univ. (Singapore)

Published in SPIE Proceedings Vol. 6672:
Advanced Characterization Techniques for Optics, Semiconductors, and Nanotechnologies III
Angela Duparré; Bhanwar Singh; Zu-Han Gu, Editor(s)

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