For the technology node of 90 nm and below, application of design for manufacturing (DFM) techniques is indispensable. We proposed the line end extension method for metal layer layouts in mask data preparation for robustness process, and achieved to reduce systematic yield loss caused by isolated patterns [1]. However, these lithography friendly design approaches sometimes cannot optimize the chip yield by increase in critical area and creating a new yield failure mechanism. In order to accurately analyze systematic yield failures and optimize layout to improve manufacturability, a set of metrics that evaluate the robustness of a layout is needed. We propose the new method to estimate systematic yield due to lithography variations on the chip layout. Lithography variations are expressed as a function of focus margin, exposure latitude and overlay misalignment, and marginal patterns at process corners in the chip layout are extracted. Each process window of the extracted patterns is calculated and common process window is calculated to achieve the full process window of the concerned patterns. The resulting process window specifications are used on the full chip to calculate systematic yield. A quantitative result of the comparison of systematic yield and random yield is shown by this method.

Date Published: 14 May 2007
PDF: 11 pages
Proc. SPIE 6607, Photomask and Next-Generation Lithography Mask Technology XIV, 660719 (14 May 2007); doi: 10.1117/12.728957

Published in SPIE Proceedings Vol. 6607:
Photomask and Next-Generation Lithography Mask Technology XIV
Hidehiro Watanabe, Editor(s)