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Proceedings Paper

FPGA realization of a split radix FFT processor
Author(s): Jesús García; Juan A. Michell; Gustavo Ruiz; Angel M. Burón
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Paper Abstract

Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to choose the algorithm and architecture to implement it. This paper explains the realization of a Split Radix FFT (SRFFT) processor based on a pipeline architecture reported before by the same authors. This architecture has as basic building blocks a Complex Butterfly and a Delay Commutator. The main advantages of this architecture are: * To combine the higher parallelism of the 4r-FFTs and the possibility of processing sequences having length of any power of two. * The simultaneous operation of multipliers and adder-subtracters implicit in the SRFFT, which leads to faster operation at the same degree of pipeline. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaining high performance at economical price and a short time of realization. The Delay Commutator has been designed to be customized for even and odd SRFFT computation levels. It can be used with segmented arithmetic of any level of pipeline in order to speed up the operating frequency. The processor has been simulated up to 350 MHz, with an EP2S15F672C3 Altera Stratix II as a target device, for a transform length of 256 complex points.

Paper Details

Date Published: 10 May 2007
PDF: 11 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65900P (10 May 2007); doi: 10.1117/12.721975
Show Author Affiliations
Jesús García, Univ. de Cantabria (Spain)
Juan A. Michell, Univ. de Cantabria (Spain)
Gustavo Ruiz, Univ. de Cantabria (Spain)
Angel M. Burón, Univ. de Cantabria (Spain)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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