New methods for visualizing process window effects on simulated lithography violations are shown. Three types of analysis of simulation errors are discussed. Worst site violations are those geometries in which at least one process condition shows largest deviations from target. For these errors, variations of Cleveland dot charts are useful for showing key attributes such pinpointing which process condition(s) cause the largest violations and the distribution of violations among focus and exposure conditions. Modifications of dot charts are also useful to visualize violations across the process window for the entire chip as opposed to selected sites. Lastly, linearity charts combined with box/whisker objects can be used to show deviations from target over a range of drawn dimensions.

Date Published: 21 March 2007
PDF: 10 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211E (21 March 2007); doi: 10.1117/12.714515

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)