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Proceedings Paper

Production-worthy OPC verification methods for protecting against process variability
Author(s): James A. Bruce; Norman Chen; Vinay Chinta; Ramon De La Cruz; Yea-Sen Lin
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Paper Abstract

In this paper we report on alternate solutions to protect against process variability - while also focusing on minimizing simulation time. We have investigated a variety of techniques, including the use of aerial image parameters to flag sites that might be sensitive to changes in dose, a mask error enhancement factor (MEEF) check based on biasing of the optical proximity correction (OPC) layer to reflect mask variations, and a sorting approach where sites with suspect parameters (e.g. high MEEF or poor aerial image quality, such as low slope) are simulated using multiple process conditions. All of these techniques represent shortcuts as compared to simulations of the full chip at multiple process conditions, and thus savings in CPU time. However, use of these short cuts can have several down-sides: first, increased risk of missing a real error, and second, increases in the number of false errors reported (where false errors are sites which are predicted to fail, but actually have an adequate window to allow for process variability). The challenge is to find methods to make the short cuts as selective as possible, so that they will flag all potentially failing sites, without flagging too many false errors.

Paper Details

Date Published: 21 March 2007
PDF: 11 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211F (21 March 2007); doi: 10.1117/12.714088
Show Author Affiliations
James A. Bruce, IBM (United States)
Norman Chen, Advanced Micro Devices, Inc. (United States)
Vinay Chinta, IBM (United States)
Ramon De La Cruz, IBM (United States)
Yea-Sen Lin, IBM (United States)

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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