
Proceedings Paper
Novel method for quality assurance of two-dimensional pattern fidelityFormat | Member Price | Non-Member Price |
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Paper Abstract
This paper proposes an evaluation pattern generating method that realizes stable printing for any two-dimensional
feature. Below 65nm design node, even in the case of using the most advanced optical techniques, the resolution limit is
approached. As a result, patterning fidelity to the target worsens in low k1 lithography conditions. Complex layout
patterns, especially two-dimensional features, become increasingly sensitive to photo-resist bridging and necking. This
means that the need for rich two-dimensional patterns is increasing in order to cope with lithographic patterning fidelity
issues, such as quality assurance of OPC script and establishment of the design rule.
A new pattern generating method reported in this paper can provide plenty of unexpected two-dimensional patterns by
employing the Monte Carlo method. It can also take the design rule checker into account to present patterns without any
design rule violation. In addition, to narrow significant patterns down to real efficient patterns, we employ a device that
generates the characteristic features of each layer.
More than 2000 feature variations of feature can be generated in less than half day by this new method and verifying
OPC with the generated 2000 patterns is estimated to be equal to verifying OPC with all pattern variations that appear in
10 real products. More examples are provided to verify the efficacy of two-dimensional patterns generated by this
approach. It is shown that the proposed method is significantly efficient for detecting hotspots that are unfaithful to the
target with low k1 factor.
Paper Details
Date Published: 21 March 2007
PDF: 10 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211B (21 March 2007); doi: 10.1117/12.713604
Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)
PDF: 10 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211B (21 March 2007); doi: 10.1117/12.713604
Show Author Affiliations
Seiji Shibazaki, Toshiba Microelectronics Corp. (Japan)
Tadashi Nakajima, Toshiba I. S. Corp. (Japan)
Tadashi Nakajima, Toshiba I. S. Corp. (Japan)
Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)
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