Share Email Print
cover

Proceedings Paper

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node
Author(s): Axel Nackaerts; Staf Verhaegen; Mircea Dusa; Hans Kattouw; Frank van Bilsen; Serge Biesemans; Geert Vandenberghe
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In this paper the impact of overlay and CD uniformity specifications on device and SRAM cell functional and parametric yield are analyzed. The variation of channel strain due to partial etching of the stress layer is determined, and we find that including this effect in the device parametric yield leads to severe CDU and overlay requirements. The method is applied to SRAM cells and memories, and it is shown that only the co-optimization of SRAM cell layout, CDU and overlay can increase the number of good dies per wafer.

Paper Details

Date Published: 21 March 2007
PDF: 11 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210N (21 March 2007); doi: 10.1117/12.713385
Show Author Affiliations
Axel Nackaerts, IMEC (Belgium)
Staf Verhaegen, IMEC (Belgium)
Mircea Dusa, ASML Netherlands B.V. (Netherlands)
Hans Kattouw, ASML Netherlands B.V. (Netherlands)
Frank van Bilsen, ASML Netherlands B.V. (Netherlands)
Serge Biesemans, IMEC (Belgium)
Geert Vandenberghe, IMEC (Belgium)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top