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Proceedings Paper

Innovative metrology for wafer edge defectivity in immersion lithography
Author(s): I. Pollentier; F. Iwamoto; M. Kocsis; A. Somanchi; F. Burkeen; S. Vedula
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Paper Abstract

In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencor's VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.

Paper Details

Date Published: 5 April 2007
PDF: 12 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65180T (5 April 2007); doi: 10.1117/12.713347
Show Author Affiliations
I. Pollentier, IMEC (Belgium)
F. Iwamoto, Matsushita Electric Industrial Co., Ltd. (Japan)
M. Kocsis, Intel Corp. (United States)
A. Somanchi, KLA-Tencor Corp. (United States)
F. Burkeen, KLA-Tencor Corp. (United States)
S. Vedula, KLA-Tencor Corp. (United States)

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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