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Proceedings Paper

Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability
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Paper Abstract

Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC manufacturer data preparation flows as k1 is pushed lower with each technology node. The use of this technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB options are explored for the gate layer by using new characterization and optimization functions available in the latest generation of correction and OPC verification tools. These include the ability to quantify across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus, exposure, and misalignment, and it is shown that significant improvements to CD control through the full manufacturing variability window can be realized.

Paper Details

Date Published: 21 March 2007
PDF: 10 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211L (21 March 2007); doi: 10.1117/12.712748
Show Author Affiliations
Travis Brist, Mentor Graphics Corp. (United States)
Le Hong, Mentor Graphics Corp. (United States)
Ayman Yehia, Mentor Graphics Corp. (United States)
Tamer Tawfik, Mentor Graphics Corp. (United States)
Shumay Shang, Mentor Graphics Corp. (United States)
Kyohei Sakajiri, Mentor Graphics Corp. (United States)
John L. Sturtevant, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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