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Proceedings Paper

Etch process monitoring by electron beam wafer inspection
Author(s): Luke Lin; Jia-Yun Chen; Wen-Yi Wong; Mark McCord; Alex Tsai; Steven Oestreich; Indranil De; Jan Lauber; Andrew Kang
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Paper Abstract

Electron beam inspection (EBI) of wafers has been widely shown to be a powerful tool for random defectivity on wafers, particularly for sub-surface electrical defects that cannot be seen by optical tools. Some types of systematic defects, such as subtle under- or over-etch of contacts, can be difficult to catch using traditional die-die or cell-cell comparison because all contacts may be similarly affected. In this paper we investigated methods for catching systematic process defects using EBI. We used a design of experiment where different dies on the same wafer were etched using a total of 4 different etch parameters. The dies were selected by using multiple resist coat, pattern, and etch steps at a single contact layer. A total of 3 wafers were given the same process treatment. Following the etch steps, one wafer continued through the fabrication process to final test, one wafer was inspected using an eS31 electron beam wafer inspection tool, while the third wafer was held in reserve. The initial inspection did not show any significant difference in defectivity between the dies, although final bit test did show pseudo-systematic defectivity depending on etch process condition. The wafer was then inspected on an eS32 tool using a special e-beam preconditioning step to enhance the contrast of subtle under-etched contacts. In this case, we were able to pick out a defectivity corresponding the etch condition of each die. The in-process defectivity found by the electron beam inspection tool matched well with the end-of-line bit failure map. In summary, subtle systematic etch process variations were detected by varying the etch process parameters across a single wafer, and tuning the electron beam inspection sensitivity to maximize contrast for subtle etch variations. Such techniques can be a powerful tool for optimization of etch process recipes to minimize wafer electrical defectivity.

Paper Details

Date Published: 5 April 2007
PDF: 7 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65182F (5 April 2007); doi: 10.1117/12.712386
Show Author Affiliations
Luke Lin, Powerchip Semiconductor Co. (Taiwan)
Jia-Yun Chen, Powerchip Semiconductor Co. (Taiwan)
Wen-Yi Wong, Powerchip Semiconductor Co. (Taiwan)
Mark McCord, KLA-Tencor (United States)
Alex Tsai, KLA-Tencor (United States)
Steven Oestreich, KLA-Tencor (United States)
Indranil De, KLA-Tencor (United States)
Jan Lauber, KLA-Tencor (United States)
Andrew Kang, KLA-Tencor (United States)

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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