Share Email Print

Proceedings Paper

Correlation length and the problem of line width roughness
Author(s): V. Constantoudis; G. P. Patsis; E. Gogolides
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The Line Width Roughness (LWR) measured by lithographers usually refers to long resist lines. On the contrary, the transferred roughness in the transistor gate (Gate Length Roughness, GLR) which is one eventually affecting transistor performance is associated with short gate widths equal to only a few multiples of CD values. Given that the most basic roughness metric, r.m.s. value Rq (or sigma), depends on the sample length at which is measured, the issue of the metrological relationship between resist (or lithographic) LWR and transistor GLR arises. The LWR parameter which seems to link these two kinds of roughness is the correlation length, since it determines the form of the curve Rq(L) describing the dependence of r.m.s. value on line length L. This paper investigates three issues relating to correlation length. The first is the precision of its measurement and it is found that the relative standard deviation of the measured values can become less than 25% provided that sufficient line lengths are included in the measurement process. Further, the measurement uncertainty is reduced when lower correlation lengths are measured. Secondly, we examine the importance of the correlation length to the electrical transistor performance and show that lower correlation lengths increase noticeably the fraction of good transistors with reliable small voltage threshold shifts independent on the used technology node and gate width. Finally, the material and process origins of correlation length variations are investigated in order to locate the appropriate changes for reducing correlation length.

Paper Details

Date Published: 5 April 2007
PDF: 10 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65181N (5 April 2007); doi: 10.1117/12.712283
Show Author Affiliations
V. Constantoudis, Institute of Microelectronics, NCSR (Greece)
G. P. Patsis, Institute of Microelectronics, NCSR (Greece)
E. Gogolides, Institute of Microelectronics, NCSR (Greece)

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?