A methodology to predict the impact of systematic manufacturing variations on the parametric behavior of standard cells in an integrated circuit is described. Such a methodology can be applied to the analysis of a full chip composed of standard cell components, and reports layout context-dependent changes in chip timing and power. For lithography and etch-induced variability, a study of a 65nm standard cell library has been done to examine the influence of cell context when looking at cell delay and leakage at different focus and exposure conditions. Cell context, or proximity effects from neighboring cells, can have a significant impact on cell performance across a process window, especially through focus, which needs to be considered for silicon-aware circuit analysis. The traditional lookup table approach used in static timing analysis or leakage power analysis needs to be augmented with an instance-specific offset for each cell in a design. Contours need to be generated for each transistor in each cell at different process points and the corresponding delay and leakage offsets should be calculated based on these contours. Electrical characterization also enables the use of other context-specific process models, such as strain and dopant fluctuations, without altering the final output. This allows subsequent tools to use the information for circuit analysis. Such a methodology is thereby useful for process-aware static timing and power analysis.

Date Published: 21 March 2007
PDF: 10 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210F (21 March 2007); doi: 10.1117/12.712281

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)