As design rules shrink, there is an unavoidable increase in the complexity of OPC/RET schemes required to enable design printability. These complex OPC/RET schemes have been facilitating unprecedented yield at k₁ factors previously deemed "unmanufacturable", but they increase the mask complexity and production cost, and can introduce yield-detracting errors. The most common errors are found in OPC design itself, and in the resulting patterning robustness across the process window. Two factors in the OPC design process that contribute to these errors are a) that 2D structures used in the design are not sufficiently well-represented in the OPC model calibration test pattern suite, and b) that the OPC model calibration is done only at the nominal process settings and not across the entire focus-exposure window. This work compares two alternative methods for calibrating OPC models. The first method uses a traditional industry flow for making CD measurements on standard calibration target structures. The second method uses 2D contour profiles extracted automatically by the CD-SEM over varying focus and exposure conditions. OPC models were developed for aggressive quadrupole illumination conditions (k₁=0.35) used in 65nm- and 45nm-node logic gate patterning. Model accuracy improvement using 2D contours for calibration through the process window is demonstrated. Additionally this work addresses the issues of automating the contour extraction and calibration process, reducing the data collection burden with improved calibration cycle time.

Date Published: 12 April 2007
PDF: 10 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65180D (12 April 2007); doi: 10.1117/12.712232

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)