
Proceedings Paper
Double patterning design split implementation and validation for the 32nm nodeFormat | Member Price | Non-Member Price |
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Paper Abstract
Single exposure capable systems for the 32nm 1/2 pitch (HP) node may not be ready in time for production. At the
possible NA of 1.35 still using water immersion lithography, one option to generate the required dense pitches is double
patterning. Here a design is printed with two separate exposures and etch steps to increase the pitch. If a 2x increase in
pitch can be achieved through the design split, double patterning could thus theoretically allow using exposure systems
conceived for the 65nm node to print 32nm node designs.
In this paper we focus on the aspect of design splitting and lithography for double patterning the poly layer of 32nm
logic cells using the Synopsys full-chip physical verification and OPC conversion platforms. All 32nm node cells have
been split in an automated fashion to target different aggressiveness towards pitch reduction and polygon cutting. Every
design split has gone through lithography optimization, Optical Proximity Correction (OPC) and Lithography Rule
Checking (LRC) at NA values of 0.93, 1.20, and 1.35. Final comparisons are based on simulations across the process
window. In addition, we have experimentally verified selected single-patterning problem areas on a 1.20 NA exposure
tool (ASML XT:1700Fi at IMEC). With this information, we establish guidelines for double patterning conversions
and present a new design rule for double patterning compliance checking applicable to full-chip scale.
Paper Details
Date Published: 21 March 2007
PDF: 15 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652109 (21 March 2007); doi: 10.1117/12.712139
Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)
PDF: 15 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652109 (21 March 2007); doi: 10.1117/12.712139
Show Author Affiliations
Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)
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