The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Date Published: 26 March 2007
PDF: 11 pages
Proc. SPIE 6520, Optical Microlithography XX, 65202P (26 March 2007);

Published in SPIE Proceedings Vol. 6520:
Optical Microlithography XX
Donis G. Flagello, Editor(s)