Share Email Print

Proceedings Paper

Lithography enhanced manufacturability analysis by using multilevel simulated contours
Author(s): Beom-Seok Seo; Woon-Hyuk Choi; Jong-Woon Park; Soung-Su Woo; Sung-Ho Lee
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Since the sub-50nm logic lithography approaches to k1 value of 0.3, it seems to be an impossible task to print typical logic patterns composed of random shapes and mixed pitches using the conventional resolution enhancement technology (RET). As one of the effective solutions to deal well with this issue, lithography friendly design (LFD) and advanced optical proximity correction (OPC) technology have been considered and developed. However, the investigation on the distortion types of various 2-dimensional patterns has rarely been preceded up to now, while lithographical hot spots are observed are dominated by the 2-dimensional patterns rather than in the 1-dimensional patterns. In order to provide a LFD layout and a good OPC performance for the future node logic device, the analysis and the hot spot's classification of the 2-dimensional pattern need to be performed. Based on our analysis of various pattern types at mimic-logic test block, a feedback strategy was implemented to reduce the 2-dimensional hot spots through the correction stage of the OPC recipes. In our study, we find out the proper value of ground rule and the cost-effective methodology which should go with reciprocal encouragement in OPC and LFD. This will give us a good methodology for the lithography technology nodes and upstream design for manufacturability (DFM) approaches.

Paper Details

Date Published: 21 March 2007
PDF: 7 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210Y (21 March 2007); doi: 10.1117/12.711825
Show Author Affiliations
Beom-Seok Seo, Samsung Electronics Co., Ltd. (South Korea)
Woon-Hyuk Choi, Samsung Electronics Co., Ltd. (South Korea)
Jong-Woon Park, Samsung Electronics Co., Ltd. (South Korea)
Soung-Su Woo, Samsung Electronics Co., Ltd. (South Korea)
Sung-Ho Lee, Samsung Electronics Co., Ltd. (South Korea)

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?