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Proceedings Paper

Inspection sensitivity improvement through optimization of lobe blocking on high-end memory devices
Author(s): Changgoo Lee; Sera Won; Daeyoung Seo; Hyeonsoo Kim; Jinwoong Kim; Jeong-Ho Yeo; Ido Dolev; Chan-Hee Kwak
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Paper Abstract

As cell size of advanced memory is approaching to around 50nm hence the size of defect is required to be detected is less than 30nm. In the array area best combinations of the inspection tool that can be achieved the maximum sensitivity through optics based are short wavelength, small pixel and collection from off-axis perspectives when the noise from pattern can be blocked. To remove the pattern noise efficiently and having enough defect signal to detector laser illumination is better approach than broadband lamp where lobe formation is not well defined and light intensity is not high enough. UVisionTM 3D channel which is off-axis collection of light from normal illumination was evaluated on array area of advanced memory design rules. Below 100nm node design rule 3D channel can successfully suppress the Customized Light Collection (CLC) lobes which are diffraction lobes from memory array pattern. In this paper we would like to report significant improvement of defect detection sensitivity through optimizing CLC lobe mask. It was developed to maximize the defect collection area and angle and showed improvements on defect detection through SNR and signal enhancement. Because of CLC lobe suppression's inverse relationship with device design rule the results show that the smaller design rule gives better defect signal detection capability.

Paper Details

Date Published: 5 April 2007
PDF: 7 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65182K (5 April 2007); doi: 10.1117/12.711742
Show Author Affiliations
Changgoo Lee, Hynix Semiconductor, Inc. (South Korea)
Sera Won, Hynix Semiconductor, Inc. (South Korea)
Daeyoung Seo, Hynix Semiconductor, Inc. (South Korea)
Hyeonsoo Kim, Hynix Semiconductor, Inc. (South Korea)
Jinwoong Kim, Hynix Semiconductor, Inc. (South Korea)
Jeong-Ho Yeo, Applied Materials (Israel)
Ido Dolev, Applied Materials (Israel)
Chan-Hee Kwak, Applied Materials (Israel)


Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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