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Proceedings Paper

Double patterning technology: process-window analysis in a many-dimensional space
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Paper Abstract

We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive images of 1/4-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces. We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling the space-width to ±10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows that overlay and etch bias are the most significant contributors to the variability of spaces. 3&sgr;[space-width] = 17% and 11% of nominal space can be achieved for 3&sgr;[Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array printed using NA=0.93.

Paper Details

Date Published: 21 March 2007
PDF: 9 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652113 (21 March 2007); doi: 10.1117/12.711515
Show Author Affiliations
Apo Sezginer, Invarium, Inc. (United States)
Bayram Yenikaya, Invarium, Inc. (United States)

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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