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Proceedings Paper

The application of SMASH alignment system for 65-55-nm logic devices
Author(s): M. Miyasaka; H. Saito; T. Tamura; T. Uchiyama; Paul Hinnen; Hyun-Woo Lee; Marc van Kemenade; Mir Shahrjerdy; Robert van Leeuwen
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Paper Abstract

65-55nm Logic-Devices require high performance of not only the resolution, of but also the overlay accuracy (Mean+3sigmas < 20-30nm). Thus, here, overlay performance of several layers in our advanced devices is investigated with using Immersion-exposure-tool. We used the new alignment system called SMASHTM which has the phase grating alignment sensor newly installed in our immersion-exposure-tool (XT1400Ei). SMASH supports flexible mark design in terms of size and pitch of the grating so that it can comply for our design requirement. SMASH has much smaller alignment beam size of ~ 40um for it. New mark design for our 65-55nm process will be investigated so as to obtain higher alignment accuracy than that of current marks. The alignment performance becomes more accurate proportionally to data density of the mark and it depends on the diffraction angle and efficiency from the mark. Thus, to obtain acceptable alignment accuracy with smaller mark, it should be designed such as diffraction efficiency is maximized within the required boundary condition in the pitch [diffraction angle] and segmentation of the mark. In this paper, several new marks are designed and evaluated. The evaluation shows that comparable performance could be obtained in the new design mark as in ASML's conventional marks. Finally, we select one from the new smaller marks and apply it to our 65-55nm process, especially, to the five process modules (Gate-to-Active, Contact-to-Gate, Metal1-to-Contact, Via1-to-Metal1, Metal2-to-Via1), and performance within 20nm (Mean+3sigmas) are typically obtained. The overlay accuracy needed for our 65-55nm Logic-Devices is successfully achieved with immersion-exposure-tool. SMASH* (SMart Alignment Sensor Hybrid): the name of alignment system using with phase grating alignment sensor.

Paper Details

Date Published: 5 April 2007
PDF: 10 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65180H (5 April 2007); doi: 10.1117/12.711059
Show Author Affiliations
M. Miyasaka, NEC Electronics Corp. (Japan)
H. Saito, NEC Electronics Corp. (Japan)
T. Tamura, NEC Electronics Corp. (Japan)
T. Uchiyama, NEC Electronics Corp. (Japan)
Paul Hinnen, ASML (Netherlands)
Hyun-Woo Lee, ASML (Netherlands)
Marc van Kemenade, ASML (Netherlands)
Mir Shahrjerdy, ASML (Netherlands)
Robert van Leeuwen, ASML (Netherlands)

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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