Proceedings Paper
An RNS public key cryptography accelerator| Format | Member Price | Non-Member Price |
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Paper Abstract
A new design of a hardware accelerator for RSA cryptography is described. The accelerator performs long integer
(1024-bit) modular exponentiation using the Residue Number System (RNS). It is implemented on an FPGA
and interfaced to a host PC via the PCI bus. The accelerator uses the RNS to break the long operands into
short channels that are processed in parallel. The performance of this architecture is evaluated and the potential
for its further improvement is discussed.
Paper Details
Date Published: 11 January 2007
PDF: 7 pages
Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641422 (11 January 2007); doi: 10.1117/12.695962
Published in SPIE Proceedings Vol. 6414:
Smart Structures, Devices, and Systems III
Said F. Al-Sarawi, Editor(s)
PDF: 7 pages
Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641422 (11 January 2007); doi: 10.1117/12.695962
Show Author Affiliations
Tom A. Coleman, The Univ. of Adelaide (Australia)
James A. Kitchener, The Univ. of Adelaide (Australia)
David L. Pudney, The Univ. of Adelaide (Australia)
James A. Kitchener, The Univ. of Adelaide (Australia)
David L. Pudney, The Univ. of Adelaide (Australia)
Kelvin D. Wauchope, The Univ. of Adelaide (Australia)
Braden J. Phillips, The Univ. of Adelaide (Australia)
Braden J. Phillips, The Univ. of Adelaide (Australia)
Published in SPIE Proceedings Vol. 6414:
Smart Structures, Devices, and Systems III
Said F. Al-Sarawi, Editor(s)
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