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Proceedings Paper

A data management layer for parallel matrix computation
Author(s): Adam Burdeniuk; Kiet To; Cheng Chew Lim
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Paper Abstract

Real-time signal processing and control applications are commonly expressed in terms of matrix or vector algorithms. This paper presents a novel decoupled architecture for these algorithms. The matrix data management layer (MDML) architecture presented separates data processing from data management. It implements functions for memory sequencing and inter-processor communications that are tuned for matrix applications. This separation allows greater flexibility in the choice of data processor to find a suitable trade-off in speed, core size, power consumption and functionality.

Paper Details

Date Published: 5 January 2007
PDF: 10 pages
Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641412 (5 January 2007); doi: 10.1117/12.695626
Show Author Affiliations
Adam Burdeniuk, The Univ. of Adelaide (Australia)
Kiet To, The Univ. of Adelaide (Australia)
Cheng Chew Lim, The Univ. of Adelaide (Australia)

Published in SPIE Proceedings Vol. 6414:
Smart Structures, Devices, and Systems III
Said F. Al-Sarawi, Editor(s)

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