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Proceedings Paper

An open source synthesisable model in VHDL of a 64-bit MIPS-based processor
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Paper Abstract

This report describes an open source VHDL description of a 64-bit MIPS-based processor. The pipeline can execute most instructions from the MIPS III instruction set architecture (ISA). The full pipeline is made available to digital VLSI engineers as a platform to test cell designs as a part of a complete computing system. The pipeline is an 8-stage RISC based on the MIPS R4000 series of processors, and includes common arithmetic operations on 32- and 64-bit operands, and full IEEE 754 floating point support. This report describes the architecture and components of the MIPS-based processor.

Paper Details

Date Published: 11 January 2007
PDF: 9 pages
Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641411 (11 January 2007);
Show Author Affiliations
Daniel R. Kelly, The Univ. of Adelaide (Australia)
Braden J. Phillips, The Univ. of Adelaide (Australia)
Said Al-Sarawi, The Univ. of Adelaide (Australia)

Published in SPIE Proceedings Vol. 6414:
Smart Structures, Devices, and Systems III
Said F. Al-Sarawi, Editor(s)

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