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Proceedings Paper

Mask specification for for wafer process optimization
Author(s): Lin Chen; Phil Freiberger; Jeff Farnsworth; Ruth Stritsman; Richard P. Rodrigues
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Paper Abstract

Mask specification has been playing ever-increasing role for wafer process optimization with tightening design rule. It is very critical to optimize specifications and sampling sizes to ensure quality as well as minimize cost and TPT for high volume manufacturing. In this paper, key parameters for mask specification affecting wafer litho process window will be discussed. Examples of how to derive key mask specification based on the litho process margin will be examined. The mask CD targeting control and plate to plate CD variation reduction strategy will be discussed.

Paper Details

Date Published: 20 October 2006
PDF: 11 pages
Proc. SPIE 6349, Photomask Technology 2006, 634917 (20 October 2006); doi: 10.1117/12.686610
Show Author Affiliations
Lin Chen, Intel Corp. (United States)
Phil Freiberger, Intel Corp. (United States)
Jeff Farnsworth, Intel Corp. (United States)
Ruth Stritsman, Intel Corp. (United States)
Richard P. Rodrigues, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 6349:
Photomask Technology 2006
Patrick M. Martin; Robert J. Naber, Editor(s)

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