Across-chip and across-wafer patterned linewidth variation (ACLV and AWLV respectively) as well as linewidth roughness (LWR) are key contributors to device performance variation. For polysilicon gate patterning, the linewidth control enabled by various phase-shift mask (PSM) design approaches is one of the key metrics in selecting the most manufacturable process. Embedded attenuated PSM (6% EAPSM), chromeless PSM (CPL) and alternating aperture PSM (AAPSM) designs were selected for comparison. Polysilicon wafers were exposed with 193nm lithography using these reticles, and then ACLV, AWLV and LWR were measured for each PSM process. The results are discussed and compared with other reticle design factors important for effective 65nm node patterning in production.

Date Published: 20 October 2006
PDF: 9 pages
Proc. SPIE 6349, Photomask Technology 2006, 63491S (20 October 2006); doi: 10.1117/12.686594

Published in SPIE Proceedings Vol. 6349:
Photomask Technology 2006
Patrick M. Martin; Robert J. Naber, Editor(s)