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Proceedings Paper

Mask complexity reduction, quality assurance, and yield improvement through reduced layout variability
Author(s): A. Balasinski; J. Cetin
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Paper Abstract

Technology, CAD, and design are increasingly more challenged by Design-for-Manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among multiple design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the RF/analog layout where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using standardized, parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, we will show that the standardized layout is the option preferred from the point of view of design, CAD, and technology.

Paper Details

Date Published: 20 October 2006
PDF: 8 pages
Proc. SPIE 6349, Photomask Technology 2006, 63490D (20 October 2006); doi: 10.1117/12.685298
Show Author Affiliations
A. Balasinski, Cypress Semiconductor (United States)
J. Cetin, Cypress Semiconductor (United States)

Published in SPIE Proceedings Vol. 6349:
Photomask Technology 2006
Patrick M. Martin; Robert J. Naber, Editor(s)

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