A novel timing recovery for read channel systems with asynchronous full-digital architecture is presented. The timing recovery consists of a frequency synthesizer and digital circuits employing an adaptive oversampling rate controller to keep its oversampling rate constant. Therefore, it is no need to change a digital equalizer characteristic even if a data transfer rate varies. Moreover, it controls the power consumption to be adequate at CAV. Since the proposed timing recovery is constructed of full-digital logic, it can realize a robust read channel system in high-speed signal processing and on next generation LSIs.

Date Published: 22 June 2006
PDF: 10 pages
Proc. SPIE 6282, Optical Data Storage 2006, 62820Y (22 June 2006); doi: 10.1117/12.685225

Published in SPIE Proceedings Vol. 6282:
Optical Data Storage 2006
Ryuichi Katayama; Tuviah E. Schlesinger, Editor(s)