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EUV mask process development and integration
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Paper Abstract

It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by introducing EUV-specific tool sets while capitalizing on the existing photomask technology and utilizing the standard photomask equipment and processes in 2004. Since then, significant progress has been made in many areas including absorber film deposition, mask patterning optimization, mask blank and patterned mask defect inspection, pattern defect repair, and EUV mask reflectivity metrology. In this paper we will present the EUV mask process with the integrated solution and the results of the mask patterning process, Ta-based in-house absorber film deposition, absorber dry etch optimization, EUV mask pattern defect inspection, absorber defect repair, and mask reflectivity performance. The EUV resist wafer print using the test masks that are fabricated in the EUV mask pilot line will be discussed as well.

Paper Details

Date Published: 20 May 2006
PDF: 10 pages
Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62830G (20 May 2006); doi: 10.1117/12.681839
Show Author Affiliations
Guojing Zhang, Intel Corp. (United States)
Pei-Yang Yan, Intel Corp. (United States)
Ted Liang, Intel Corp. (United States)
Yan Du, Intel Corp. (United States)
Peter Sanchez, Intel Corp. (United States)
Seh-jin Park, Intel Corp. (United States)
Eric J. Lanzendorf, Intel Corp. (United States)
Chang Ju Choi, Intel Corp. (United States)
Emily Y. Shu, Intel Corp. (United States)
Alan R. Stivers, Intel Corp. (United States)
Jeff Farnsworth, Intel Corp. (United States)
Kangmin Hsia, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)
Michael J. Leeson, Intel Corp. (United States)
Gilroy Vandentop, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 6283:
Photomask and Next-Generation Lithography Mask Technology XIII
Morihisa Hoga, Editor(s)

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