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Proceedings Paper

A novel approach to implementing geometric transformations in FPGAs
Author(s): W. Larry Herald; Paul R. Mackin; Charles M. Niswonger; Rhoe Thompson; George C. Goldsmith II
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Paper Abstract

Recent advances in Field-Programmable Gate Arrays (FPGAs) and innovations in firmware design have allowed more complex image processing algorithms to be implemented entirely within the FPGA devices while substantially improving performance and reducing development time. Firmware innovations include a unique memory buffer architecture and the use of floating-point math. The design discussed takes advantage of these advances and innovations to implement a geometric transformation algorithm with bilinear interpolation for applications such as distortion correction. The firmware and hardware developed in this effort support image sizes of up to 1024x1024 pixels at 200 Hz and pixel rates of 216 MHz with versions available that support oversized input images.

Paper Details

Date Published: 16 May 2006
PDF: 10 pages
Proc. SPIE 6208, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XI, 620815 (16 May 2006); doi: 10.1117/12.669299
Show Author Affiliations
W. Larry Herald, MacAulay-Brown, Inc. (United States)
Paul R. Mackin, Air Force Research Lab. (United States)
Charles M. Niswonger, L3 Communications (United States)
Rhoe Thompson, Air Force Research Lab. (United States)
George C. Goldsmith II, Air Force Research Lab. (United States)

Published in SPIE Proceedings Vol. 6208:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XI
Robert Lee Murrer Jr., Editor(s)

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