Microprocessor performance is now limited by the poor delay and bandwidth performance of the on-chip global wiring layers. Although relatively few in number, the global metal wires have proven to be the primary cause of performance limitations - effectively leading to a premature saturation of Moore's Law scaling in future Silicon generations. Building upon device-, circuit-, system- and architectural-level models, a framework for performance evaluation of global wires is developed aimed at quantifying the major challenges faced by intrachip global communications over the span of six technology generations. This paper reviews the status of possible intra-chip optical interconnect solutions in which the Silicon chip's global metal wiring layers are replaced with a high-density guided-wave or free-space optical interconnection fabric. The overall goal is to provide a scalable approach that is compatible with established silicon chip fabrication and packaging technology, and which can extend the reach of Moore's Law for many generations to come. To achieve the required densities, the integrated sources are envisioned to be modulators that are optically powered by off-chip sources. Structures for coupling dense modulator arrays to optical power sources and to free-space or guide-wave optical global fabrics are analyzed. Results of proof-of-concept experiments, which demonstrate the potential benefits of ultra-high-density optical interconnection fabrics for intra-chip global communications, are presented.

Date Published: 28 February 2006
PDF: 15 pages
Proc. SPIE 6126, Photonics Packaging and Integration VI, 61260A (28 February 2006); doi: 10.1117/12.661293

Published in SPIE Proceedings Vol. 6126:
Photonics Packaging and Integration VI
Allen M. Earman; Ray T. Chen, Editor(s)