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Proceedings Paper

Immersion lithography robustness for the C065 node
Author(s): Scott Warrick; Rob Morton; Andrea Mauri; Jean-Damien Chapon; Jerome Belledent; Will Conley; Alex Barr; Kevin Lucas; Cedric Monget; Valerie Plantier; David Cruau; Juan-Manuel Gomez; Emmanuel Sicurani; Jan-Willem Gemmink
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Paper Abstract

Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (hp90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (hp65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).

Paper Details

Date Published: 15 March 2006
PDF: 12 pages
Proc. SPIE 6154, Optical Microlithography XIX, 615407 (15 March 2006); doi: 10.1117/12.657158
Show Author Affiliations
Scott Warrick, Freescale Semiconductors (France)
Rob Morton, Philips Semiconductors (France)
Andrea Mauri, STMicroelectronics (France)
Jean-Damien Chapon, STMicroelectronics (France)
Jerome Belledent, Philips Semiconductors (France)
Will Conley, Freescale Semiconductors (France)
Alex Barr, Freescale Semiconductors (France)
Kevin Lucas, Freescale Semiconductors (France)
Cedric Monget, STMicroelectronics (France)
Valerie Plantier, Philips Semiconductors (France)
David Cruau, Freescale Semiconductors (France)
Juan-Manuel Gomez, Freescale Semiconductors (France)
Emmanuel Sicurani, CEA (France)
Jan-Willem Gemmink, Philips Semiconductors (France)

Published in SPIE Proceedings Vol. 6154:
Optical Microlithography XIX
Donis G. Flagello, Editor(s)

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