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Proceedings Paper

The use of process models to enhance device performance through semiconductor design
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Paper Abstract

As semiconductor manufacturing nodes march towards increasingly aggressive process nodes, the features that can be manufactured on a silicon wafer are becoming more and more constrained. These constraints are arising from the need for manufacturing process margin, the result of which is improved yields and wafer throughput. For less aggressive process nodes, these constraints have been transferred between the design and manufacturing communities using tables of design rules. However, as process nodes march forward, these are rules are getting complex and unmanageable. A better methodology to communicate design rules is to build a model of the manufacturing process for use by the design team. This model can then be used to analyze a piece of layout for manufacturing robustness, and allow the design to make informed layout revisions. Design rules encompass effects due to many manufacturing processes including exposure, registration, etch, reticle construction, electro migration, etc. In order to create useful design rules, all of these processes must be understood and combined into a set of process rules. In order to reduce the complexity of the design rules table, a process model may be applied in complex pattern configurations. This study will seek to understand the definition of complex configurations for photolithography design rules, and it will attempt to demonstrate the usefulness of model-based design rules.

Paper Details

Date Published: 14 March 2006
PDF: 8 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560J (14 March 2006); doi: 10.1117/12.656964
Show Author Affiliations
Lawrence S. Melvin III, Synopsys, Inc. (United States)
Daniel Zhang, Synopsys, Inc. (United States)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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