In this paper we propose an alternative sub-100nm manufacturing flow using reconfigurable OPC technology. In this flow, an initial full-chip OPC is performed similar to the conventional approach. But when errors are found during verification - which can include checks across the process window - we optimize the OPC results locally with reconfigurable OPC technology without disturbing the OPC results elsewhere in the design. Creating optimized local solutions for LRC errors offers a more manufacturable solution, and it virtually guarantees rapid and correct OPC convergence. These chip-specific solutions can then be retained for future runs and the results analyzed for inclusion in the global or "master" recipe.

Date Published: 20 March 2006
PDF: 8 pages
Proc. SPIE 6154, Optical Microlithography XIX, 61543D (20 March 2006); doi: 10.1117/12.656708

Published in SPIE Proceedings Vol. 6154:
Optical Microlithography XIX
Donis G. Flagello, Editor(s)