Share Email Print

Proceedings Paper

Hot spot management in ultra-low k1 lithography
Author(s): Kohji Hashimoto; Satoshi Usui; Shigeki Nojima; Satoshi Tanaka; Eiji Yamanaka; Soichi Inoue
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

We have constructed a hot spot management flow for LSI manufacturing in the ultra-low k1 lithography era. This flow involves three main management steps: hot spot reduction, hot spot extraction and hot spot monitoring. Hot spot reduction works for lithography friendly restriction (RDR) and manufacturability check (MC). Hot spot extraction is carried out with consideration of short turn-around-time (TAT), accurate extraction and convenient functions such as hot spot for interlayers. Hot spot monitoring is achieved with tolerance-based verification in mask fabrication process and wafer process (lithography and etching). These technology elements were integrated into the actual LSI fabrication flow. The application of this concept to LSI manufacturing could contribute to reduction of total cost, quick TAT and ramp up to volume production.

Paper Details

Date Published: 13 March 2006
PDF: 12 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560N (13 March 2006); doi: 10.1117/12.656418
Show Author Affiliations
Kohji Hashimoto, Toshiba Corp. (Japan)
Satoshi Usui, Toshiba Corp. (Japan)
Shigeki Nojima, Toshiba Corp. (Japan)
Satoshi Tanaka, Toshiba Corp. (Japan)
Eiji Yamanaka, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?