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Proceedings Paper

2D parallel optical interconnects between CMOS ICs
Author(s): O. Rits; M. De Wilde; G. Roelkens; R. Bockstaele; Richard Annen; Martin Bossard; Francois Marion; R. Baets
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Paper Abstract

The CMOS IC industry thrives on the down-scaling drive for ever smaller transistors, leading to faster, smaller and more complex digital systems. These ICs are interconnected by electrical tracks running on Printed Circuit Boards. Due to different frequency-dependent sources of signal degradation, the performance of these electrical interconnects lags behind the IC performance. As the electrical interconnect bottleneck increasingly impacts overall system performance, the interest in optical interconnects at the inter-chip level is growing. An important question to answer is how and where such optical interconnects should be implemented. Therefore, we first discuss the weaknesses of electrical interconnects and the potential benefits of optical interconnects. From this we then consider the implications on the introduction of optical interconnects and we argue why integration is of key importance for the successful introduction of optical interconnects at this level. Finally we describe how we have implemented optical inter-chip interconnects in a demonstrator system and go into more detail on the different levels of integration in this demonstrator system.

Paper Details

Date Published: 3 March 2006
PDF: 12 pages
Proc. SPIE 6124, Optoelectronic Integrated Circuits VIII, 61240L (3 March 2006); doi: 10.1117/12.652108
Show Author Affiliations
O. Rits, Ghent Univ., IMEC (Belgium)
M. De Wilde, Ghent Univ., IMEC (Belgium)
G. Roelkens, Ghent Univ., IMEC (Belgium)
R. Bockstaele, Ghent Univ., IMEC (Belgium)
Richard Annen, Helix AG (Switzerland)
Martin Bossard, Helix AG (Switzerland)
Francois Marion, CEA-LETI (France)
R. Baets, Ghent Univ., IMEC (Belgium)

Published in SPIE Proceedings Vol. 6124:
Optoelectronic Integrated Circuits VIII
Louay A. Eldada; El-Hang Lee, Editor(s)

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