Share Email Print

Proceedings Paper

A real-time asymmetric multiprocessor reconfigurable system-on-chip architecture
Author(s): Xin Xie; John A. Williams; Neil W. Bergmann
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed.

Paper Details

Date Published: 5 January 2006
PDF: 12 pages
Proc. SPIE 6035, Microelectronics: Design, Technology, and Packaging II, 603508 (5 January 2006); doi: 10.1117/12.638216
Show Author Affiliations
Xin Xie, The Univ. of Queensland (Australia)
John A. Williams, The Univ. of Queensland (Australia)
Neil W. Bergmann, The Univ. of Queensland (Australia)

Published in SPIE Proceedings Vol. 6035:
Microelectronics: Design, Technology, and Packaging II
Alex J. Hariz, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?