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Proceedings Paper

First 65nm tape-out using inverse lithography technology (ILT)
Author(s): Chi-Yuan Hung; Bin Zhang; Deming Tang; Eric Guo; Linyong Pang; Yong Liu; Andrew Moore; Kechang Wang
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Paper Abstract

This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.

Paper Details

Date Published: 5 November 2005
PDF: 9 pages
Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 59921U (5 November 2005); doi: 10.1117/12.632415
Show Author Affiliations
Chi-Yuan Hung, Semiconductor International Manufacturing Corp. (China)
Bin Zhang, Semiconductor International Manufacturing Corp. (China)
Deming Tang, Semiconductor International Manufacturing Corp. (China)
Eric Guo, Semiconductor International Manufacturing Corp. (China)
Linyong Pang, Luminescent Technologies, Inc. (United States)
Yong Liu, Luminescent Technologies, Inc. (United States)
Andrew Moore, Luminescent Technologies, Inc. (United States)
Kechang Wang, Luminescent Technologies, Inc. (United States)

Published in SPIE Proceedings Vol. 5992:
25th Annual BACUS Symposium on Photomask Technology
J. Tracy Weed; Patrick M. Martin, Editor(s)

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