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Proceedings Paper

Through-process window resist modelling strategies for the 65 nm node
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Paper Abstract

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist, they have often a large number of parameters to fit and suffer from long computing times to execute the simulations. Simplified resist models are thus needed to enhance run-time computing during simulation. The objective of this study is to test the predictability of such resist models across the process window. Two different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific simulations obtained with the two different techniques are compared against experimental results.

Paper Details

Date Published: 4 November 2005
PDF: 10 pages
Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 599219 (4 November 2005); doi: 10.1117/12.632096
Show Author Affiliations
Amandine Borjon, Philips Semiconductors (France)
Freescale Semiconductor (France)
LETI-CEA (France)
Jerôme Belledent, Philips Semiconductors (France)
Yorick Trouiller, LETI-CEA (France)
Kyle Patterson, Freescale Semiconductor (France)
Kevin Lucas, Freescale Semiconductor (France)
Christophe Couderc, Philips Semiconductors (France)
Frank Sundermann, STMicroelectronics (France)
Jean-Christophe Urbani, STMicroelectronics (France)
Stanislas Baron, STMicroelectronics (France)
Yves Rody, Philips Semiconductors (France)
Christian Gardin, Freescale Semiconductor (France)
Franck Foussadier, STMicroelectronics (France)
Patrick Schiavone, LTM-CNRS (France)

Published in SPIE Proceedings Vol. 5992:
25th Annual BACUS Symposium on Photomask Technology
J. Tracy Weed; Patrick M. Martin, Editor(s)

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