Mask data file sizes are increasing as we move from technology generation to generation. The historical 30% linear shrink every 2-3 years that has been called Moore's Law, has driven a doubling of the transistor budget and hence feature count. The transition from steppers to step-and-scan tools has increased the area of the mask that needs to be patterned. At the 130nm node and below, Optical Proximity Correction (OPC) has become prevalent, and the edge fragmentation required to implement OPC leads to an increase in the number of polygons required to define the layout. Furthermore, Resolution Enhancement Techniques (RETs) such as Sub-Resolution Assist Features (SRAFs) or tri-tone Phase Shift Masks (PSM) require additional features to be defined on the mask which do not resolve on the wafer, further increasing masks volumes. In this paper we review historical data on mask file sizes for microprocessor designs. We consider the consequences of this increase in file size on Mask Data Prep (MDP) activities, both within the Integrated Device Manufacturer (IDM) and Mask Shop, namely: computer resources, storage and networks (for file transfer). The impact of larger file sizes on mask writing times is also reviewed. Finally we consider, based on the trends that have been observed over the last 5 technology nodes, what will be required to maintain reasonable MDP and mask manufacturing cycle times.

Date Published: 4 November 2005
PDF: 11 pages
Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 599211 (4 November 2005); doi: 10.1117/12.629369

Published in SPIE Proceedings Vol. 5992:
25th Annual BACUS Symposium on Photomask Technology
J. Tracy Weed; Patrick M. Martin, Editor(s)