Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks (GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise implementation of Simulink behavioural model accounting for the saturation of frequency control voltage is therefore developed for the BMCDR, and the parameters of the circuit blocks can be readily adjusted and optimized based on the behavioural model. The newly designed BMCDR utilizes the 0.18um standard CMOS technology and is shown to be capable of operating at bit rate of 2.5Gbps, as well as the recovery time of one bit period in our simulation. The developed behaviour model is verified by comparing with the detailed circuit simulation.

Date Published: 13 October 2005
PDF: 10 pages
Proc. SPIE 5970, Photonic Applications in Devices and Communication Systems, 59702W (13 October 2005); doi: 10.1117/12.628728

Published in SPIE Proceedings Vol. 5970:
Photonic Applications in Devices and Communication Systems
Peter Mascher; John C. Cartledge; Andrew Peter Knights; David V. Plant, Editor(s)