We report simulation results for a directional coupler between silicon waveguides in different layers of a three-dimensional (3D) optical circuit. The coupling length is 1.4 mm. The device is manufacturable using standard CMOS technology provided individual waveguide layers can be vertically stacked. In simulations of coupling efficiency the design exhibits negligible loss with respect to translational and rotational misalignments of up to 0.5 μm. Efficiency degradation is less than 5% for etch depth and waveguide width variations of 0.4 μm, and less than 1 dB over the range of standard lithographic tolerances for variations from layer to layer in feature width, depth, and alignment.

Date Published: 12 October 2005
PDF: 10 pages
Proc. SPIE 5970, Photonic Applications in Devices and Communication Systems, 59700G (12 October 2005); doi: 10.1117/12.627884

Published in SPIE Proceedings Vol. 5970:
Photonic Applications in Devices and Communication Systems
Peter Mascher; John C. Cartledge; Andrew Peter Knights; David V. Plant, Editor(s)