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Proceedings Paper

The application of phase grating to CLM technology for the sub-65nm node optical lithography
Author(s): Gi-Sung Yoon; Sung-Hyuck Kim; Ji-Soong Park; Sun-Young Choi; Chan-Uk Jeon; In-Kyun Shin; Sung-Woon Choi; Woo-Sung Han
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Paper Abstract

As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k1 has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSM's. For the low-k1 lithography, we have researched CLM technique as a good solution especially for sub-65nm node. As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with pattern's pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field. We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer. Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.

Paper Details

Date Published: 28 June 2005
PDF: 11 pages
Proc. SPIE 5853, Photomask and Next-Generation Lithography Mask Technology XII, (28 June 2005); doi: 10.1117/12.617201
Show Author Affiliations
Gi-Sung Yoon, SAMSUNG Electronics (South Korea)
Sung-Hyuck Kim, SAMSUNG Electronics (South Korea)
Ji-Soong Park, SAMSUNG Electronics (South Korea)
Sun-Young Choi, SAMSUNG Electronics (South Korea)
Chan-Uk Jeon, SAMSUNG Electronics (South Korea)
In-Kyun Shin, SAMSUNG Electronics (South Korea)
Sung-Woon Choi, SAMSUNG Electronics (South Korea)
Woo-Sung Han, SAMSUNG Electronics (South Korea)

Published in SPIE Proceedings Vol. 5853:
Photomask and Next-Generation Lithography Mask Technology XII
Masanori Komuro, Editor(s)

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