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Proceedings Paper

FPGA-based high-performance arithmetic pipeline synthesis for DSP applications
Author(s): Albert A. Liddicoat; Shawn Cary; Jackson Pang
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Paper Abstract

Today FPGAs are used in many digital signal processing applications. In order to design high-performance area efficient DSP pipelines various arithmetic functions and algorithms must be used. In this work, FPGA-based functional units for Cosine, Arctangent, and the Square Root functions are designed using bipartite tables and iterative algorithms. The bipartite tabular approach was four to 12 times faster than the iterative approach but requires 8-40 times more FPGA hardware resources to implement these functions. Next, these functions along with the FPGA hardware multipliers and a reciprocal bipartite table unit are used for hardware rectangular-to-polar and polar-to-rectangular conversion macro-functions. These macro-functions allow for a 7-10 times performance improvement for the high-performance pipelines or an area reduction of 9-17 times for the low cost implementations. In addition, software tool to design FPGA based DSP pipelines using the Cosine, Sine, Arctangent, Square Root, and Reciprocal units with the hardware multipliers is presented.

Paper Details

Date Published: 16 September 2005
PDF: 8 pages
Proc. SPIE 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV, 59100R (16 September 2005); doi: 10.1117/12.615338
Show Author Affiliations
Albert A. Liddicoat, California Polytechnic State Univ. (United States)
Shawn Cary, California Polytechnic State Univ. (United States)
Jackson Pang, California Polytechnic State Univ. (United States)

Published in SPIE Proceedings Vol. 5910:
Advanced Signal Processing Algorithms, Architectures, and Implementations XV
Franklin T. Luk, Editor(s)

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