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Proceedings Paper

Hardware acceleration and verification of systems designed with hardware description languages (HDL)
Author(s): Remigiusz Wisniewski; Marek Wegrzyn
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Paper Abstract

Hardware description languages (HDLs) allow creating bigger and bigger designs nowadays. The size of prototyped systems very often exceeds million gates. Therefore verification process of the designs takes several hours or even days. The solution for this problem can be solved by hardware acceleration of simulation.

Paper Details

Date Published: 23 February 2005
PDF: 12 pages
Proc. SPIE 5775, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments III, (23 February 2005); doi: 10.1117/12.610689
Show Author Affiliations
Remigiusz Wisniewski, Univ. of Zielona Gora (Poland)
Marek Wegrzyn, Univ. of Zielona Gora (Poland)


Published in SPIE Proceedings Vol. 5775:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments III
Ryszard S. Romaniuk, Editor(s)

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